Excessive Bandwidth Memory

Excessive Bandwidth Memory Wave Routine (HBM) is a computer memory interface for 3D-stacked synchronous dynamic random-entry memory (SDRAM) initially from Samsung, AMD and SK Hynix. RAM in upcoming CPUs, and FPGAs and in some supercomputers (such because the NEC SX-Aurora TSUBASA and Fujitsu A64FX). HBM achieves larger bandwidth than DDR4 or GDDR5 whereas utilizing less energy, and in a considerably smaller kind issue. This is achieved by stacking as much as eight DRAM dies and an non-obligatory base die which may embrace buffer circuitry and test logic. The stack is usually connected to the memory controller on a GPU or CPU via a substrate, similar to a silicon interposer. Alternatively, the memory die might be stacked instantly on the CPU or GPU chip. Inside the stack the dies are vertically interconnected by by-silicon vias (TSVs) and microbumps. The HBM technology is analogous in precept but incompatible with the Hybrid Memory Cube (HMC) interface developed by Micron Expertise. HBM memory bus could be very wide compared to other DRAM reminiscences akin to DDR4 or GDDR5.



An HBM stack of 4 DRAM dies (4-Hello) has two 128-bit channels per die for a complete of eight channels and a width of 1024 bits in total. A graphics card/GPU with four 4-Hello HBM stacks would due to this fact have a memory bus with a width of 4096 bits. In comparison, the bus width of GDDR memories is 32 bits, with 16 channels for a graphics card with a 512-bit memory interface. HBM helps as much as four GB per bundle. The bigger number of connections to the memory, relative to DDR4 or GDDR5, required a new technique of connecting the HBM memory to the GPU (or other processor). AMD and Nvidia have both used function-constructed silicon chips, called interposers, to connect the memory and GPU. This interposer has the added advantage of requiring the memory and processor to be physically shut, decreasing memory paths. Nevertheless, as semiconductor system fabrication is significantly costlier than printed circuit board manufacture, this provides value to the ultimate product.



The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into impartial channels. The channels are completely independent of each other and aren't essentially synchronous to each other. The HBM DRAM makes use of a wide-interface architecture to realize excessive-pace, low-power operation. Each channel interface maintains a 128-bit data bus operating at double knowledge fee (DDR). HBM helps switch charges of 1 GT/s per pin (transferring 1 bit), yielding an overall bundle bandwidth of 128 GB/s. The second technology of High Bandwidth Memory, Memory Wave HBM2, additionally specifies as much as eight dies per stack and doubles pin switch rates as much as 2 GT/s. Retaining 1024-bit extensive access, Memory Wave HBM2 is in a position to reach 256 GB/s memory bandwidth per package deal. The HBM2 spec permits up to 8 GB per bundle. HBM2 is predicted to be especially useful for performance-delicate shopper functions akin to digital actuality. On January 19, 2016, Samsung introduced early mass production of HBM2, at up to 8 GB per stack.



In late 2018, JEDEC introduced an update to the HBM2 specification, offering for increased bandwidth and capacities. As much as 307 GB/s per stack (2.5 Tbit/s efficient information rate) is now supported within the official specification, although merchandise operating at this speed had already been accessible. Additionally, the update added support for 12-Hi stacks (12 dies) making capacities of up to 24 GB per stack potential. On March 20, 2019, Samsung introduced their Flashbolt HBM2E, featuring eight dies per stack, a switch rate of 3.2 GT/s, offering a complete of sixteen GB and 410 GB/s per stack. August 12, 2019, SK Hynix introduced their HBM2E, featuring eight dies per stack, a transfer price of 3.6 GT/s, offering a complete of sixteen GB and 460 GB/s per stack. On July 2, 2020, SK Hynix introduced that mass manufacturing has begun. In October 2019, Samsung introduced their 12-layered HBM2E. In late 2020, Micron unveiled that the HBM2E customary could be up to date and alongside that they unveiled the following normal generally known as HBMnext (later renamed to HBM3).